Adaptive Beamforming for Radar: Floating-Point QRD+WBS in an FPGA (WP452)

The gradual transition of analog signal processing to the digital domain in radar and radio systems has led to advancements in beamforming techniques and, consequently, to new applications. The ability to steer beams digitally with great precision has radically changed the future of commercial and military radar system design. Adaptive beamforming algorithms have pushed the signal processing world into the use of floating-point arithmetic; this has increased radar capability by allowing creation of multiple simultaneous spot beams for individual real-time target tracking. The modif ied Gram-Schmidt (MGS) QR decomposition (QRD) and weight back substitution (WBS), key algorithms for radar DSP, allow a radar to form beams adaptively while suppressing side lobes, noise, and jamming. These applications require a very high number of FLOPS (floating-point operations per second). Xilinx FPGAs have an orders-of-magnitude advantage in floating-point performance compared to commercial GPU, DSP, and multi-core CPUs. High-Level Synthesis (HLS), a standard tool in the Xilinx Vivado® Design Suite, supports native C language design. A floating-point matrix inversion algorithm, the heart of adaptive beamforming, can now be coded in native C/C++ or SystemC using Xilinx Vivado HLS. The design described in this white paper was completed in about four hours. Hand-coding a VHDL/Verilog version of this design and verifying it using RTL could take weeks or even months, depending on the skill of the designer. Using HLS, Xilinx FPGA adaptive beamforming performance and QoR can be increased by orders of magnitude and power consumption greatly decreased compared to existing GPU and multi-core processor designs. This white paper focuses on a complex floating-point, variable-sized MGS QRD+WBS, up to 128x64 in size.